1. Field of the Invention
The present invention relates to a probe card for testing integrated circuit chips. More particularly, the present invention relates to a probe card for testing the electrical characteristics of at least two Quad Pad chips at the same time.
2. Description of the Related Art
Generally speaking, various kinds of processing steps are involved in the fabrication of semiconductor devices. These processes can be roughly divided into those for forming integrated circuits on a wafer by repeatedly carrying out a step of producing a specific pattern on the wafer, and those associated with the assembly of the devices including a process of slicing the wafer into unit chips and a process of packaging the chips.
Before the wafer is sliced into unit chips, the electrical characteristics of each portion of a wafer corresponding to a unit chip is tested by an Electrical Die Sorting (EDS) process.
The EDS process is used to examine all of the chips formed on the wafer so that inferior chips can be reworked or removed prior to their assembly into the semiconductor devices. Thus, EDS aims to save the assembly costs associated with forming semiconductor devices from defective or inferior chips.
The EDS process is carried out using a probe card. U.S. Pat. No. 5,412,329 discloses a conventional one of such probe cards as fully illustrated in FIG. 4. FIG. 1 shows the conventional testing apparatus making use of the probe card.
Referring now to FIG. 1, the testing apparatus includes a test section 3, and a loading/unloading device 2 for transporting a wafer 20 to be examined from a cassette (not shown) into the test section 3. The test section 3 encloses a stage 9 on which the wafer 20 is mounted, and a lower CCD (Charge Coupled Device) camera 8. The test apparatus also includes a test head 7, and an upper CCD camera 6 disposed over the test section 3. The test head 7 is connected to a testing module 5 which is backed-up by a CPU 4. A probe card having a printed circuit board 12 and a plurality of pins 10 is detachably mounted to the lower surface of the test head 7 by means of a holder (not shown). The probe card faces a wafer 20 mounted on the stage 9 disposed within the test section 3. The stage 9 can be driven in X, Y and Z directions and about an axis .theta. according to control signals generated by the CPU 4 on the basis of signals received by the CPU 4 from the upper and lower CCD cameras 6, 8.
When the testing apparatus is used, a certain electrical signal is applied from the testing module 5 through the pins 10 to the chips on the wafer 20. A signal from the integrated circuits (ICs) on the chips is then transferred back to the testing module 5. The CPU 4 can determine whether the ICs conform to design parameters based on the signals received by the testing module 5.
Meanwhile, with the development of high-speed devices such as semiconductor memory devices, etc., and of compact chips, the layout of the chips in modern semiconductor devices is changing rapidly. Current layouts include the so-called quad-pad or fine-pitch types. In addition, EDS testing has been improved beyond its original ability to test only one wafer at a time. Now, EDS apparatus have been designed to perform multi-parallel testing such as dual testing, quad testing, octal testing, and hexa-testing.
FIG. 2 illustrates a conventional probe card of an EDS testing apparatus designed to carry out a conventional dual test. The probe card is removably mounted on the test head by means of a holder. The probe card includes a printed circuit board 12, and a plurality of pins 10 integrated with the circuit board 12. The printed circuit board 12 has an aperture 11 extending through an inner central portion thereof so that the contact of the pins 10 with contact pads 22 (see FIG. 4) of the chips being tested can be observed by the upper CCD camera 6.
The probe card shown in FIG. 2 is a dual test probe card which is intended to test, at the same time, the electrical characteristics of at least two chips disposed at a first test chip location T1 and a second test chip location T2, respectively. Also, the probe card shown in FIG. 2 is designed to test a quad-pad type of chip having a plurality of contact pads located along all four of its sides.
FIG. 3 shows a portion of a wafer 20 forming a plurality of unit chips 24. Each of the unit chips 24 is to be provided with an IC to form a quad-pad type of chip testable by the probe card of FIG. 2. The unit chips 24 of the wafer 20 are thus provided with a plurality of contact pads 22 along each of four edges thereof, which edges will become the peripheral edge of the quad-pad type of chip. Once the ICs are formed on the unit chips 24, the chips will be EDS tested by placing the contact pads 22 in contact with the pins 10 of the probe card. Once the EDS testing is completed, the wafer 20 is sliced along the scribe lines 26 to separate the chips from one another. Thereafter, the chips are packaged to complete the production of the semiconductor devices.
Referring again to FIG. 4, a frame comprising the pins 10 is soldered to the printed circuit board (PCB) 12. The PCB 12 has a test circuit pattern 13 configured in accordance with the EDS testing to be conducted. The number and location of the ends of the pins 10 correspond to those of the contact pads 22. An insulating fixing ring 14 extends around the aperture 11 of the PCB 12 at the bottom surface of the PCB 12. The pins 10 are attached to the fixing ring 14 by electrically insulative epoxy resin 16.
Each of several characteristics of the probe card can greatly affect the EDS test. These characteristics include the tip length "b" of the pins 10 (the length of the bent tips of the pin which contact the contact pads 22), the angle "a" at which the tips subtend with the portions of the pins from which the tips are bent, an incident angle "c" of the pins 10, the pin diameter "d", and the pin extension length "e" (the horizontal distance between the location where the pins are held fixed by the fixing ring 14 and the pin tips).
Referring back to FIG. 2, most of the pins 10 extend from locations all lying in the same horizontal plane as fixed together by the fixing ring (not visible) disposed at the lower surface of the print circuit board 12. However, those pins 10 which are to contact the contact pads 22 close to the region lying between the first test chip location T1 and the second test chip location T2, are arranged vertically as shown in FIG. 5 and FIG. 6.
For this group of pins 10, the tip length varies from a tip length `b1` (the length of the pin tip lying closest to the fixing ring 14) to a tip length `b9` (the length of the pin tip located on the middle of the group).
FIG. 7 shows the allocation of the pins 10 of the conventional probe card used in carrying out a quad test (in the drawing, the printed circuit board is omitted). This probe card is designed to test four chips at the same time, and as with the probe card shown in FIG. 2 for use in carrying out the dual test, the pins 10 which are to contact the contact pads lying at the regions between the first test chip location T1 and the second test chip location T2, and between the second test chip location T2 and the third test chip location T3, and between the third test chip location T3 chip location and the fourth test chip location T4, are vertically mounted to the fixing ring 14.
Therefore, this probe card has several portions in which pins are arranged vertically as shown in FIG. 5 and 6.
Accordingly, like the probe card shown in FIG. 2, this probe card has pin characteristics, such as pin tip length, which vary. Because, as mentioned above, such characteristics can affect the EDS test, the varying characteristics compromise the reliability of the EDS test.
In addition, the contact resistance of the pins becomes greater the further up one goes in the multi-layered vertical structure thereof. Such a wide variation in the values of the contact resistance of the pins also compromises the reliability of the EDS test to the point where the test can yield widely different results when testing the same lot of wafers a number of different times.
In addition, the unstable contact provided by the pins of the conventional probe card produce conditions during testing which result in the need to clean the tips of the pins frequently. This limits the efficiency with which the EDS testing can be carried out.